1. Technical Field
The present invention relates to circuit design verification, and more specifically, to circuit design verification using zero-delay simulation.
2. Related Art
Zero-delay simulation is typically used to verify a circuit design. However, if (a) the circuit design comprises components operating according to different, asynchronous clocks and (b) the circuit design is vulnerable to glitches, the simulation result does not correctly reflect the behavior of the actual circuit built from the circuit design. Therefore, there is a need for a zero-delay simulation method that improves the simulation result of the prior art.